1. Field of the Invention
The present invention relates in general to a dual microprocessor control system and pertains, more particularly, to dual microprocessor control in an asynchronous data communication system preferably employing a receive microprocessor and a transmit microprocessor.
2. Description of the Prior Art
In a data communications system employing a telephone PBX, line data rates may vary from 300 to 19,200 bits per second. At a rate of 19,200 bits per second, with 16 channels operating, this means that a character is to be supplied for transmission each 52.1 microseconds. Similarly, a character may be received each 52.1 microseconds. With such data volume requirements, it is typical to employ a pair of microprocessors. One microprocessor is dedicated to transmitting signals and the other is dedicated to receiving signals. Even with the use of these dual microprocessors this still allows only a small amount of time for control tasks such as packetizing/depacketizing data, handling modem status update messages, call processing, etc.
In addition to the specific tasks of transmitting and receiving for the respective transmit microprocessor and receive microprocessor, it is also desired that the transmit and receive microprocessors be able to communicate with each other. When the two processors interchange information, it is desired to de-race the communications. This is usually carried out with interrupt-driven techniques employing "mailboxes" and "locks". However, such an interrupt-driven system is relatively slow in operation. For pertinent prior art refer to U.S. Pat. No. 4,482,982 granted Nov. 13, 1984, to Yu et al. and U.S. Pat. No. 4,488,231 granted Dec. 11, 1984, to Yu et al., both owned by the present assignee herein.
Accordingly, it is an object of the present invention to provide an improved dual microprocessor control system in which the efficiency of intercommunication between processors is substantially improved.